ENGG * 3190 – Logic Synthesis W (3-2) [0.50]

This course presents automatic logic synthesis techniques for computer-aided design (CAD) of very large-scale integrated (VLSI) circuits and systems. Topics covered are: two-level Boolean network optimization, multi-level Boolean network optimization, technology mapping for library-based designs and field-programmable gate-array (FPGA) designs, and state-assignment and re-timing for sequential circuits. The course will also cover various representations of Boolean functions such as binary decision diagrams (BDDs) and discuss their applications to logic synthesis. (First offering – Winter 2013)

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